“From 5G to industrial applications, as more and more data is collected, transmitted, and stored, the performance limits of analog signal processing devices are constantly expanding, some reaching gigasamples per second. As the pace of innovation never slows, next-generation Electronic solutions will enable further reductions in solution size, continued improvements in power efficiency, and higher requirements for noise performance.
“
By: Patrick Errgy Pasaquian, Senior Applications Engineer, Analog Devices; Pablo Perez, Jr., Senior Applications Engineer
Introduction
From 5G to industrial applications, as more and more data is collected, transmitted, and stored, the performance limits of analog signal processing devices are constantly expanding, some reaching gigasamples per second. As the pace of innovation never slows, next-generation electronic solutions will enable further reductions in solution size, continued improvements in power efficiency, and higher requirements for noise performance.
One might think that noise generated in each power domain (analog, digital, serial digital, and digital input-output (I/O)) should be minimized or isolated for good dynamic performance, but the pursuit of absolute minimum noise may diminishing returns to research. How does a designer know if the noise performance of a power supply is adequate? The first step is to quantify the sensitivity of the device so that the power supply spectral output matches this power domain requirement. Knowledge is power: saving design time by avoiding overdesign can go a long way in designing.
This article outlines how to quantify the power supply noise sensitivity of a load in a signal processing chain and how to calculate the maximum acceptable power supply noise. Measurement setup is also discussed. Finally, we discuss some strategies for meeting power domain sensitivity and real-world power supply noise requirements. Subsequent articles in this series will delve into the details of how to optimize the power distribution network (PDN) for ADCs, DACs, and RF transceivers.
Understand and quantify the sensitivity of signal processing loads to power supply noise
The first step in power supply optimization is to investigate and analyze the true sensitivity of analog signal processing devices to power supply noise. These include understanding the impact of power supply noise on key dynamic performance specifications, and characterizing power supply noise sensitivity — namely, power supply modulation ratio (PSMR) and power supply rejection ratio (PSRR).
PSMR and PSRR indicate good power supply rejection characteristics, but they alone are not sufficient to determine how low the ripple should be. This article describes how to use PSMR and PSRR to determine the ripple margin threshold or maximum allowable power supply noise. Optimal power system design is only possible by determining the thresholds that match the spectral output of the power supply. Optimizing the power supply will not degrade the dynamic performance of each analog signal processing device if it is ensured that the power supply noise is below its maximum specification.
Effects of Power Supply Noise on Analog Signal Processing Devices
The effect of power supply noise on analog signal processing devices should be understood. These effects can be quantified by three measurement parameters:
► Spurious Free Dynamic Range (SFDR)
► Signal to Noise Ratio (SNR)
► Phase Noise (PN)
Understanding the effect of power supply noise on these parameters is the first step in optimizing power supply noise specifications.
Spurious Free Dynamic Range (SFDR)
Power supply noise can couple into the carrier signal of any analog signal processing system. The effect of power supply noise depends on its strength relative to the carrier signal in the frequency domain. One measure is SFDR, which represents the smallest signal that can be distinguished from a large interfering signal—specifically, the ratio of the amplitude of the carrier signal to the amplitude of the highest spurious signal, regardless of where it is in the spectrum The following formula:
carrier signal
spurious signal
SFDR = Spurious Free Dynamic Range (dB)
carrier signal = rms value of carrier signal amplitude (peak or full scale)
Spurious = RMS value of the highest spurious amplitude in the spectrum
Figure 1. SFDR of the AD9208 high-speed ADC using both (a) clean power supplies and (b) noisy power supplies.
SFDR can be specified relative to full scale (dBFS) or carrier signal (dBc). Coupling of power supply ripple to the carrier signal can create interfering spurs that degrade SFDR. Figure 1 compares the SFDR performance of the AD9208 high-speed ADC with clean and noisy power supplies. In this case, when 1 MHz power supply ripple appears near the carrier frequency of the ADC’s fast Fourier transform (FFT) spectral output as a modulation spur, the power supply noise reduces the SFDR by about 10 dB.
Signal to Noise Ratio (SNR)
SFDR is determined by the highest spur in the spectrum, while SNR is determined by the total noise in the spectrum. SNR limits the ability of an analog signal processing system to identify low amplitude signals and is theoretically limited by the resolution of the converters in the system. SNR is mathematically defined as the ratio of the carrier signal level to the sum of all noise spectral components (except the first five harmonics and DC), where:
carrier signal
spurious signal
SNR = Signal to Noise Ratio (dB)
carrier signal = rms value of the carrier signal (peak or full scale)
Spectral noise = rms sum of all noise spectral components except the first five harmonics
Noise power supplies reduce SNR by coupling in the carrier signal and adding noise spectral components to the output spectrum. As shown in Figure 2, the SNR of the AD9208 high-speed ADC is reduced from 56.8 dBFS to 51.7 dBFS when 1 MHz power supply ripple creates a spectral noise component in the FFT output spectrum.
Phase Noise (PN)
Phase noise is a measure of the frequency stability of a signal. Ideally, an oscillator should be able to generate a specific set of stable frequencies over a period of time. But in the real world, there are always some small disturbance amplitude and phase fluctuations in the signal. These phase fluctuations, or jitters, are distributed on both sides of the signal in the frequency spectrum.
Phase noise can be defined in several ways. In this paper, phase noise is defined as single-sideband (SSB) phase noise, a commonly used definition that uses the ratio of the power density of the carrier signal offset frequency to the total power of the carrier signal, where:
Sideband Power Density
carrier power
SSB PN = single sideband phase noise (dBc/Hz)
Sideband Power Density = Noise Power per 1 Hz Bandwidth at Carrier Signal Offset Frequency (W/Hz)
Carrier Power = Total Carrier Power (W)
Figure 2. SNR of the AD9208 high-speed ADC using (a) a clean power supply and (b) a noisy power supply.
Figure 3. (a) Two different power supplies with significantly different output noise levels.
(b) Phase noise performance of the ADRV9009 when powered by these two supplies separately.
For analog signal processing devices, voltage noise coupled into the device clock through the clock supply voltage can create phase noise that affects the frequency stability of the internal local oscillator (LO). This expands the range of LO frequencies in the spectrum, increasing the power density at the offset frequency corresponding to the carrier, thereby increasing phase noise.
Figure 3 compares the phase noise performance of the ADRV9009 transceiver when powered by two different power supplies. Figure 3a shows the noise spectrum of the two power supplies, and Figure 3b shows the resulting phase noise. Both supplies are based on the LTM8063 µModule with spread spectrum (SSFM)®Stabilizer. The advantage of SSFM is that by distributing the fundamental frequency over a range, it improves the noise performance of the converter’s fundamental switching frequency and its harmonics. This can be seen in Figure 3a—note the relatively broad noise peaks at 1 MHz and its harmonics. A trade-off to consider is that the SSFM’s triangular wave modulation frequency produces noise below 100 kHz — note that the peaks start around 2 kHz.
The backup power supply adds a low-pass filter to reject noise above 1 MHz, and an ADP1764 low dropout (LDO) post-regulator to reduce the overall noise floor, especially below 10 kHz (mainly SSFM generated noise). The overall power supply noise is improved due to the additional filtering, which enhances the phase noise performance below the 10 kHz offset frequency, as shown in Figure 3b.
Power Supply Noise Sensitivity of Analog Signal Processing Devices
The sensitivity of a load to power supply ripple can be quantified by two parameters:
► Power Supply Rejection Ratio (PSRR)
► Power Supply Modulation Ratio (PSMR)
Power Supply Rejection Ratio (PSRR)
PSRR represents the ability of the device to attenuate noise from the power supply pins over a range of frequencies. Generally, there are two types of PSRR: static (DC) PSRR and dynamic (AC) PSRR. DC PSRR is a measure of the change in output offset due to changes in the DC supply voltage. This is of little concern as the power system should provide a regulated DC voltage to the load. On the other hand, AC PSRR represents the ability of a device to reject AC signals in a DC power supply over a range of frequencies.
AC PSRR is determined by injecting a sine wave signal at the power supply pins of the device and observing the error spurs that appear on the data converter/transceiver output spectral noise floor at the injection frequency (Figure 4). AC PSRR is defined as the ratio of the measured injected signal amplitude to the corresponding error spur amplitude on the output spectrum, where:
inject ripple
error spur
Error spurs = magnitude of spurs in the output spectrum due to injected ripple
Injected Ripple = Amplitude of the sine wave coupled and measured at the input supply pin
Figure 4. Error spurs in the output spectrum of an analog signal processing device due to power supply ripple.
Figure 5 shows a block diagram of a typical PSRR setup. Using the AD921310 GSPS high-speed ADC as an example, a 1 MHz, 13.3 mV peak-to-peak sine wave is actively coupled on a 1.0 V analog supply rail. A corresponding 1 MHz digitized spur appears above the ADC’s C108 dBFS FFT spectral noise floor. The 1 MHz digitized spur is C81 dBFS, which corresponds to a peak-to-peak voltage of 124.8 μV, referenced to an analog input full-scale range of 1.4 V peak-to-peak. Using Equation 4 to calculate the ac PSRR at 1 MHz, the ac PSRR at 1 MHz is 40.5 dB. Figure 6 shows the ac PSRR of the AD9213 1.0 V AVDD rail.
Figure 5. Simplified block diagram of the PSRR/PSMR test setup.
Figure 6. AD9213 High Speed ADC AC PSRR for 1.0 V AVDD Rail.
Power Supply Modulation Ratio (PSMR)
PSMR affects analog signal processing devices differently than PSRR. PSMR represents the sensitivity of the device to power supply noise when modulated with an RF carrier signal. This effect can be seen as modulation spurs applied to the device around the carrier frequency, manifesting as carrier sidebands.
Power supply modulation is achieved by combining the input ripple signal with a clean DC voltage using a line injector/coupling circuit. Power supply ripple is injected into the power supply pins from the signal generator as a sine wave signal. A sine wave modulated to an RF carrier produces sideband spurs with an offset frequency equal to the sine wave frequency. The spurious level is affected by the amplitude of the sine wave and the sensitivity of the device. The simplified PSMR test setup is the same as that of PSRR, shown in Figure 5, but the output mainly shows the carrier frequency and its sideband spurs, as shown in Figure 7. PSMR is defined as the ratio of the amplitude of the power injected ripple to the amplitude of the modulation sideband spurs around the carrier, where:
inject ripple
Modulation spurs
Modulation spurs = amplitude of carrier frequency sideband spurs due to injected ripple
Injected Ripple = Amplitude of the sine wave coupled and measured at the input supply pin
Figure 7. Modulation sideband spurs in the carrier signal due to power supply ripple.
Assume that the AD917512.6 GSPS high-speed DAC is operating at a 100 MHz carrier, actively coupled to the 1.0 V AVDD rail with approximately 3.05 mV peak-to-peak 10 MHz supply ripple. A corresponding 24.6 μV peak-to-peak modulation spur appears in the sideband of the carrier signal, with an offset frequency equal to the power supply ripple frequency of about 10 MHz. Using Equation 5 to calculate the PSMR at 10 MHz yields 41.9 dB. Figure 8 shows the AD9175 1.0V AVDD rail PSMR for channel DAC0 at various carrier frequencies.
Figure 8. AD9175 High Speed DAC PSMR for 1.0 V AVDD Rail (Channel DAC0).
Determining the Maximum Allowable Power Supply Ripple
The PSMR can be combined with the reference threshold of the powered device to determine the maximum allowable voltage ripple for each power domain of the analog signal processing device. The reference threshold itself can be one of several values and represents the allowable level of spurs (caused by power supply ripple) that the device can tolerate without significantly affecting its dynamic performance. This spurious level can be the spurious-free dynamic range (SFDR), the percentage of least significant bits (LSB), or the output spectral noise floor. Equation 6 shows the maximum allowable input ripple (VR_MAX) as a function of PSMR and the measured noise floor of each device, where:
threshold
VR_MAX = maximum allowable voltage ripple on each supply rail before spurs are generated in the output spectral noise floor
PSMR = Noise Sensitivity of Target Power Rail (dB)
Threshold = predefined reference threshold (in this case, the output spectral noise floor)
For example, the output spectral noise floor of the AD9175 is about 1 μV peak-to-peak. The PSMR of a 1800 MHz carrier with 10 MHz ripple is about 20.9 dB. Using Equation 6, the maximum allowable ripple that can be tolerated in the device supply pins without degrading its dynamic performance is 11.1 μV peak-to-peak.
Figure 9 shows the LT8650S step-down Silent Switcher®Combined result of the spectral output of the regulator (with and without the output LC filter) and the maximum allowable ripple on the AD9175 1.0 V AVDD rail. The regulator spectral output contains spurs at the fundamental switching frequency and its harmonics. The LT8650S directly powering the AD9175 produces a fundamental frequency that exceeds the maximum allowable threshold, resulting in modulation sideband spurs in the output spectrum, as shown in Figure 10. Simply adding an LC filter can reduce the switching spurs below the maximum allowable ripple, as shown in Figure 11.
Figure 9. LT8650S power supply spectral output versus maximum allowable voltage ripple on the 1.0 V AVDD rail.
Figure 10. AD9175 DAC0 Output Spectrum at 1800 MHz Carrier Frequency
(Output directly to AVDD rail using LT8650S DC-DC Silent Switcher converter).
Figure 11. Output spectrum of AD9175 DAC0 at 1800 MHz carrier frequency (using LT8650S with LC filter power supply).
in conclusion
The excellent dynamic performance of high-speed analog signal processing devices is easily compromised by power supply noise. To avoid system performance degradation, it is necessary to fully understand the sensitivity of the signal chain to power supply noise. This can be determined by setting the maximum allowable ripple, which is critical for power distribution network (PDN) design. Once the maximum allowable ripple threshold is known, various methods can be used to design an optimized power supply. If the maximum allowable ripple is well-margined, the PDN will not degrade the dynamic performance of high-speed analog signal processing devices.
References
Delos, Peter, “Power Modulation Ratio Demystified: How Is PSMR Different From PSRR?” Analog Devices, Inc., December 2018.
Delos, Peter and Jarrett Liner. “Improved DAC Phase Noise Measurement Enables Ultra-Low Phase Noise DDS Applications.” Analog Dialogue, Volume 51, Issue 3, August 2017.
“A Basic Guide to Data Transformation.” Analog Devices
Umesh Jayamohan. “Powering a GSPS or RF Sampling ADC: Switches and LDOs,” Analog Devices, Inc., November 2015.
Limjoco, Aldrick, Patrick Errgy Pasaquian and Jefferson Eco. “Silent Switcher µModule Regulator Provides Low-Noise Power to GSPS Sampling ADCs and Saves Half the Space.” Analog Devices, Inc., October 2018.
Naeem, Naveed and Samantha Fontaine. “PSRR Characterization of Data Acquisition μModule Devices with Internal Bypass Capacitors.” Analog Dialogue, Volume 54, Issue 3, July 2020.
“From 5G to industrial applications, as more and more data is collected, transmitted, and stored, the performance limits of analog signal processing devices are constantly expanding, some reaching gigasamples per second. As the pace of innovation never slows, next-generation Electronic solutions will enable further reductions in solution size, continued improvements in power efficiency, and higher requirements for noise performance.
“
By: Patrick Errgy Pasaquian, Senior Applications Engineer, Analog Devices; Pablo Perez, Jr., Senior Applications Engineer
Introduction
From 5G to industrial applications, as more and more data is collected, transmitted, and stored, the performance limits of analog signal processing devices are constantly expanding, some reaching gigasamples per second. As the pace of innovation never slows, next-generation electronic solutions will enable further reductions in solution size, continued improvements in power efficiency, and higher requirements for noise performance.
One might think that noise generated in each power domain (analog, digital, serial digital, and digital input-output (I/O)) should be minimized or isolated for good dynamic performance, but the pursuit of absolute minimum noise may diminishing returns to research. How does a designer know if the noise performance of a power supply is adequate? The first step is to quantify the sensitivity of the device so that the power supply spectral output matches this power domain requirement. Knowledge is power: saving design time by avoiding overdesign can go a long way in designing.
This article outlines how to quantify the power supply noise sensitivity of a load in a signal processing chain and how to calculate the maximum acceptable power supply noise. Measurement setup is also discussed. Finally, we discuss some strategies for meeting power domain sensitivity and real-world power supply noise requirements. Subsequent articles in this series will delve into the details of how to optimize the power distribution network (PDN) for ADCs, DACs, and RF transceivers.
Understand and quantify the sensitivity of signal processing loads to power supply noise
The first step in power supply optimization is to investigate and analyze the true sensitivity of analog signal processing devices to power supply noise. These include understanding the impact of power supply noise on key dynamic performance specifications, and characterizing power supply noise sensitivity — namely, power supply modulation ratio (PSMR) and power supply rejection ratio (PSRR).
PSMR and PSRR indicate good power supply rejection characteristics, but they alone are not sufficient to determine how low the ripple should be. This article describes how to use PSMR and PSRR to determine the ripple margin threshold or maximum allowable power supply noise. Optimal power system design is only possible by determining the thresholds that match the spectral output of the power supply. Optimizing the power supply will not degrade the dynamic performance of each analog signal processing device if it is ensured that the power supply noise is below its maximum specification.
Effects of Power Supply Noise on Analog Signal Processing Devices
The effect of power supply noise on analog signal processing devices should be understood. These effects can be quantified by three measurement parameters:
► Spurious Free Dynamic Range (SFDR)
► Signal to Noise Ratio (SNR)
► Phase Noise (PN)
Understanding the effect of power supply noise on these parameters is the first step in optimizing power supply noise specifications.
Spurious Free Dynamic Range (SFDR)
Power supply noise can couple into the carrier signal of any analog signal processing system. The effect of power supply noise depends on its strength relative to the carrier signal in the frequency domain. One measure is SFDR, which represents the smallest signal that can be distinguished from a large interfering signal—specifically, the ratio of the amplitude of the carrier signal to the amplitude of the highest spurious signal, regardless of where it is in the spectrum The following formula:
carrier signal
spurious signal
SFDR = Spurious Free Dynamic Range (dB)
carrier signal = rms value of carrier signal amplitude (peak or full scale)
Spurious = RMS value of the highest spurious amplitude in the spectrum
Figure 1. SFDR of the AD9208 high-speed ADC using both (a) clean power supplies and (b) noisy power supplies.
SFDR can be specified relative to full scale (dBFS) or carrier signal (dBc). Coupling of power supply ripple to the carrier signal can create interfering spurs that degrade SFDR. Figure 1 compares the SFDR performance of the AD9208 high-speed ADC with clean and noisy power supplies. In this case, when 1 MHz power supply ripple appears near the carrier frequency of the ADC’s fast Fourier transform (FFT) spectral output as a modulation spur, the power supply noise reduces the SFDR by about 10 dB.
Signal to Noise Ratio (SNR)
SFDR is determined by the highest spur in the spectrum, while SNR is determined by the total noise in the spectrum. SNR limits the ability of an analog signal processing system to identify low amplitude signals and is theoretically limited by the resolution of the converters in the system. SNR is mathematically defined as the ratio of the carrier signal level to the sum of all noise spectral components (except the first five harmonics and DC), where:
carrier signal
spurious signal
SNR = Signal to Noise Ratio (dB)
carrier signal = rms value of the carrier signal (peak or full scale)
Spectral noise = rms sum of all noise spectral components except the first five harmonics
Noise power supplies reduce SNR by coupling in the carrier signal and adding noise spectral components to the output spectrum. As shown in Figure 2, the SNR of the AD9208 high-speed ADC is reduced from 56.8 dBFS to 51.7 dBFS when 1 MHz power supply ripple creates a spectral noise component in the FFT output spectrum.
Phase Noise (PN)
Phase noise is a measure of the frequency stability of a signal. Ideally, an oscillator should be able to generate a specific set of stable frequencies over a period of time. But in the real world, there are always some small disturbance amplitude and phase fluctuations in the signal. These phase fluctuations, or jitters, are distributed on both sides of the signal in the frequency spectrum.
Phase noise can be defined in several ways. In this paper, phase noise is defined as single-sideband (SSB) phase noise, a commonly used definition that uses the ratio of the power density of the carrier signal offset frequency to the total power of the carrier signal, where:
Sideband Power Density
carrier power
SSB PN = single sideband phase noise (dBc/Hz)
Sideband Power Density = Noise Power per 1 Hz Bandwidth at Carrier Signal Offset Frequency (W/Hz)
Carrier Power = Total Carrier Power (W)
Figure 2. SNR of the AD9208 high-speed ADC using (a) a clean power supply and (b) a noisy power supply.
Figure 3. (a) Two different power supplies with significantly different output noise levels.
(b) Phase noise performance of the ADRV9009 when powered by these two supplies separately.
For analog signal processing devices, voltage noise coupled into the device clock through the clock supply voltage can create phase noise that affects the frequency stability of the internal local oscillator (LO). This expands the range of LO frequencies in the spectrum, increasing the power density at the offset frequency corresponding to the carrier, thereby increasing phase noise.
Figure 3 compares the phase noise performance of the ADRV9009 transceiver when powered by two different power supplies. Figure 3a shows the noise spectrum of the two power supplies, and Figure 3b shows the resulting phase noise. Both supplies are based on the LTM8063 µModule with spread spectrum (SSFM)®Stabilizer. The advantage of SSFM is that by distributing the fundamental frequency over a range, it improves the noise performance of the converter’s fundamental switching frequency and its harmonics. This can be seen in Figure 3a—note the relatively broad noise peaks at 1 MHz and its harmonics. A trade-off to consider is that the SSFM’s triangular wave modulation frequency produces noise below 100 kHz — note that the peaks start around 2 kHz.
The backup power supply adds a low-pass filter to reject noise above 1 MHz, and an ADP1764 low dropout (LDO) post-regulator to reduce the overall noise floor, especially below 10 kHz (mainly SSFM generated noise). The overall power supply noise is improved due to the additional filtering, which enhances the phase noise performance below the 10 kHz offset frequency, as shown in Figure 3b.
Power Supply Noise Sensitivity of Analog Signal Processing Devices
The sensitivity of a load to power supply ripple can be quantified by two parameters:
► Power Supply Rejection Ratio (PSRR)
► Power Supply Modulation Ratio (PSMR)
Power Supply Rejection Ratio (PSRR)
PSRR represents the ability of the device to attenuate noise from the power supply pins over a range of frequencies. Generally, there are two types of PSRR: static (DC) PSRR and dynamic (AC) PSRR. DC PSRR is a measure of the change in output offset due to changes in the DC supply voltage. This is of little concern as the power system should provide a regulated DC voltage to the load. On the other hand, AC PSRR represents the ability of a device to reject AC signals in a DC power supply over a range of frequencies.
AC PSRR is determined by injecting a sine wave signal at the power supply pins of the device and observing the error spurs that appear on the data converter/transceiver output spectral noise floor at the injection frequency (Figure 4). AC PSRR is defined as the ratio of the measured injected signal amplitude to the corresponding error spur amplitude on the output spectrum, where:
inject ripple
error spur
Error spurs = magnitude of spurs in the output spectrum due to injected ripple
Injected Ripple = Amplitude of the sine wave coupled and measured at the input supply pin
Figure 4. Error spurs in the output spectrum of an analog signal processing device due to power supply ripple.
Figure 5 shows a block diagram of a typical PSRR setup. Using the AD921310 GSPS high-speed ADC as an example, a 1 MHz, 13.3 mV peak-to-peak sine wave is actively coupled on a 1.0 V analog supply rail. A corresponding 1 MHz digitized spur appears above the ADC’s C108 dBFS FFT spectral noise floor. The 1 MHz digitized spur is C81 dBFS, which corresponds to a peak-to-peak voltage of 124.8 μV, referenced to an analog input full-scale range of 1.4 V peak-to-peak. Using Equation 4 to calculate the ac PSRR at 1 MHz, the ac PSRR at 1 MHz is 40.5 dB. Figure 6 shows the ac PSRR of the AD9213 1.0 V AVDD rail.
Figure 5. Simplified block diagram of the PSRR/PSMR test setup.
Figure 6. AD9213 High Speed ADC AC PSRR for 1.0 V AVDD Rail.
Power Supply Modulation Ratio (PSMR)
PSMR affects analog signal processing devices differently than PSRR. PSMR represents the sensitivity of the device to power supply noise when modulated with an RF carrier signal. This effect can be seen as modulation spurs applied to the device around the carrier frequency, manifesting as carrier sidebands.
Power supply modulation is achieved by combining the input ripple signal with a clean DC voltage using a line injector/coupling circuit. Power supply ripple is injected into the power supply pins from the signal generator as a sine wave signal. A sine wave modulated to an RF carrier produces sideband spurs with an offset frequency equal to the sine wave frequency. The spurious level is affected by the amplitude of the sine wave and the sensitivity of the device. The simplified PSMR test setup is the same as that of PSRR, shown in Figure 5, but the output mainly shows the carrier frequency and its sideband spurs, as shown in Figure 7. PSMR is defined as the ratio of the amplitude of the power injected ripple to the amplitude of the modulation sideband spurs around the carrier, where:
inject ripple
Modulation spurs
Modulation spurs = amplitude of carrier frequency sideband spurs due to injected ripple
Injected Ripple = Amplitude of the sine wave coupled and measured at the input supply pin
Figure 7. Modulation sideband spurs in the carrier signal due to power supply ripple.
Assume that the AD917512.6 GSPS high-speed DAC is operating at a 100 MHz carrier, actively coupled to the 1.0 V AVDD rail with approximately 3.05 mV peak-to-peak 10 MHz supply ripple. A corresponding 24.6 μV peak-to-peak modulation spur appears in the sideband of the carrier signal, with an offset frequency equal to the power supply ripple frequency of about 10 MHz. Using Equation 5 to calculate the PSMR at 10 MHz yields 41.9 dB. Figure 8 shows the AD9175 1.0V AVDD rail PSMR for channel DAC0 at various carrier frequencies.
Figure 8. AD9175 High Speed DAC PSMR for 1.0 V AVDD Rail (Channel DAC0).
Determining the Maximum Allowable Power Supply Ripple
The PSMR can be combined with the reference threshold of the powered device to determine the maximum allowable voltage ripple for each power domain of the analog signal processing device. The reference threshold itself can be one of several values and represents the allowable level of spurs (caused by power supply ripple) that the device can tolerate without significantly affecting its dynamic performance. This spurious level can be the spurious-free dynamic range (SFDR), the percentage of least significant bits (LSB), or the output spectral noise floor. Equation 6 shows the maximum allowable input ripple (VR_MAX) as a function of PSMR and the measured noise floor of each device, where:
threshold
VR_MAX = maximum allowable voltage ripple on each supply rail before spurs are generated in the output spectral noise floor
PSMR = Noise Sensitivity of Target Power Rail (dB)
Threshold = predefined reference threshold (in this case, the output spectral noise floor)
For example, the output spectral noise floor of the AD9175 is about 1 μV peak-to-peak. The PSMR of a 1800 MHz carrier with 10 MHz ripple is about 20.9 dB. Using Equation 6, the maximum allowable ripple that can be tolerated in the device supply pins without degrading its dynamic performance is 11.1 μV peak-to-peak.
Figure 9 shows the LT8650S step-down Silent Switcher®Combined result of the spectral output of the regulator (with and without the output LC filter) and the maximum allowable ripple on the AD9175 1.0 V AVDD rail. The regulator spectral output contains spurs at the fundamental switching frequency and its harmonics. The LT8650S directly powering the AD9175 produces a fundamental frequency that exceeds the maximum allowable threshold, resulting in modulation sideband spurs in the output spectrum, as shown in Figure 10. Simply adding an LC filter can reduce the switching spurs below the maximum allowable ripple, as shown in Figure 11.
Figure 9. LT8650S power supply spectral output versus maximum allowable voltage ripple on the 1.0 V AVDD rail.
Figure 10. AD9175 DAC0 Output Spectrum at 1800 MHz Carrier Frequency
(Output directly to AVDD rail using LT8650S DC-DC Silent Switcher converter).
Figure 11. Output spectrum of AD9175 DAC0 at 1800 MHz carrier frequency (using LT8650S with LC filter power supply).
in conclusion
The excellent dynamic performance of high-speed analog signal processing devices is easily compromised by power supply noise. To avoid system performance degradation, it is necessary to fully understand the sensitivity of the signal chain to power supply noise. This can be determined by setting the maximum allowable ripple, which is critical for power distribution network (PDN) design. Once the maximum allowable ripple threshold is known, various methods can be used to design an optimized power supply. If the maximum allowable ripple is well-margined, the PDN will not degrade the dynamic performance of high-speed analog signal processing devices.
References
Delos, Peter, “Power Modulation Ratio Demystified: How Is PSMR Different From PSRR?” Analog Devices, Inc., December 2018.
Delos, Peter and Jarrett Liner. “Improved DAC Phase Noise Measurement Enables Ultra-Low Phase Noise DDS Applications.” Analog Dialogue, Volume 51, Issue 3, August 2017.
“A Basic Guide to Data Transformation.” Analog Devices
Umesh Jayamohan. “Powering a GSPS or RF Sampling ADC: Switches and LDOs,” Analog Devices, Inc., November 2015.
Limjoco, Aldrick, Patrick Errgy Pasaquian and Jefferson Eco. “Silent Switcher µModule Regulator Provides Low-Noise Power to GSPS Sampling ADCs and Saves Half the Space.” Analog Devices, Inc., October 2018.
Naeem, Naveed and Samantha Fontaine. “PSRR Characterization of Data Acquisition μModule Devices with Internal Bypass Capacitors.” Analog Dialogue, Volume 54, Issue 3, July 2020.
The Links: 6MBP150RA060 DGA32240-25
