Connector design solves data rate and density challenges

As the demand for bandwidth continues to increase, so does the demand for higher data rates in the system. Once 1 to 3Gbps, then switched to 4 to 8 Gbps, now we are close to 28 Gbps, and expect to enter 56G. This trend was recently promoted to DesignCon 2018, and many exhibitors showed off the interconnection PAM 4 running at 112 Gbps.

As the demand for bandwidth continues to increase, so does the demand for higher data rates in the system. Once 1 to 3Gbps, then switched to 4 to 8 Gbps, now we are close to 28 Gbps, and expect to enter 56G. This trend was recently promoted to DesignCon 2018, and many exhibitors showed off the interconnection PAM 4 running at 112 Gbps.

Connector design solves data rate and density challenges

Although the data communications and telecommunications industries are working hard to promote these cutting-edge data rates, achieving this performance is far more difficult than it sounds. Design challenges include routing complexity on the PCB and the potential demand for higher layer counts. For longer trace lengths, more peculiar PCB materials with lower dielectric constant and retimer can be used to reduce degraded signal loss. All these factors will increase the cost of the system.

In addition to materials and costs, designers often face the challenge of reducing the size of the finished product. The proliferation of mobile and handheld devices is driving this trend, as well as new requirements in industries such as telecommunications, high-power computers, medical equipment, aerospace and defense, and even industrial applications.

Connector design solves data rate and density challenges

In addition, the new high-data-rate chipsets (designed to generate as little heat as possible, of course) still generate heat. These usually require more and larger heat sinks, which further complicates the design dilemma.

Obviously, the growing demand for smaller, higher-bandwidth PCBs is driving R&D in the interconnect industry. Sales of fine pitch and high-speed interconnection systems have grown steadily. An interesting reminder is that most high-speed interconnects are also fine pitch. However, the smaller the interconnect pitch, the more difficult it is to achieve higher bandwidth.

Smaller and tighter pitch interconnect systems have brought a series of new electrical challenges, such as crosstalk and insertion loss. This is mainly due to the fact that one differential pair is too close to the next, thereby reducing wiring space and reducing ground pins.

As with many design challenges, there are several ways to solve this problem:

PCB layout

Designers can alleviate these problems by strategically considering the layout of their circuit boards. Carefully planned trace design and routing, grounding positions, vias, etc. can increase the PCB data rate. PCB design strategies are beyond the scope of this article, but there are plenty of tools, resources, and people to assist in this work. For example, Samtec owns Signal Integrity Group and Teraspeed Consulting to help solve these problems.

High-speed fine pitch interconnection design

Although there are conflicts between miniaturization and higher data rate goals, connector manufacturers can strike a balance between performance and footprint.
An example of these connector design strategies is the contact called EdgeRate®. The contact is designed for higher cycle applications while adapting to higher bandwidth. For example, the 0.8mm pitch edge rate interconnect is rated at 56 Gbps PAM4. One way to achieve this balance between bandwidth and spacing is to design and place pins in the plastic body. Specifically, the thin and narrow cutting edges that Edge Rage touches are placed side by side. This minimizes the parallel surface area, which reduces broadside coupling and crosstalk.

Connector design solves data rate and density challenges

Improve connector performance

Other connector design strategies used to achieve high-bandwidth fine-pitch interconnects include, but are not limited to:

・ Perform multiple simulation cycles in the early stages of the design to accurately quantify product performance before starting expensive manufacturing processes.
・ When the connectors are mated, minimize the via stub in the contact area. From a mechanical point of view, the longer the via stub, the better the reliability, but the via stub is an electrical load like an antenna.
・ Simplify contact geometry to improve signal path performance.
・ Shorten the lead length to minimize the distance the signal must travel.
・ Include asymmetrical positions and contacts as much as possible; alternate design reduces paired crosstalk between pin rows and between rows. In other words, the footprint should drive the connector performance.
・ Optimize the connector branch area (BOR). Think of the connector as the key node in the link; focus not only on the node, but also on the link.
・ When space permits, insert a common ground plane into the connector.

Plastic molded products will obviously affect the performance of the connector. Among other issues, we carefully consider the following attributes:
・ High temperature plastic suitable for RoHS
・ Match Dk to obtain the required impedance control
・ Dimensional stability of temperature and time

Most importantly, the shorter and straighter the signal path (contact with the connector), the better the signal integrity performance. But the balance function is that the connector must have sufficient positive force and pull-out force, as well as a certain degree of sturdiness. The latter considerations usually degrade signal integrity performance.

As the demand for bandwidth continues to increase, so does the demand for higher data rates in the system. Once 1 to 3Gbps, then switched to 4 to 8 Gbps, now we are close to 28 Gbps, and expect to enter 56G. This trend was recently promoted to DesignCon 2018, and many exhibitors showed off the interconnection PAM 4 running at 112 Gbps.

As the demand for bandwidth continues to increase, so does the demand for higher data rates in the system. Once 1 to 3Gbps, then switched to 4 to 8 Gbps, now we are close to 28 Gbps, and expect to enter 56G. This trend was recently promoted to DesignCon 2018, and many exhibitors showed off the interconnection PAM 4 running at 112 Gbps.

Connector design solves data rate and density challenges

Although the data communications and telecommunications industries are working hard to promote these cutting-edge data rates, achieving this performance is far more difficult than it sounds. Design challenges include routing complexity on the PCB and the potential demand for higher layer counts. For longer trace lengths, more peculiar PCB materials with lower dielectric constant and retimer can be used to reduce degraded signal loss. All these factors will increase the cost of the system.

In addition to materials and costs, designers often face the challenge of reducing the size of the finished product. The proliferation of mobile and handheld devices is driving this trend, as well as new requirements in industries such as telecommunications, high-power computers, medical equipment, aerospace and defense, and even industrial applications.

Connector design solves data rate and density challenges

In addition, the new high-data-rate chipsets (designed to generate as little heat as possible, of course) still generate heat. These usually require more and larger heat sinks, which further complicates the design dilemma.

Obviously, the growing demand for smaller, higher-bandwidth PCBs is driving R&D in the interconnect industry. Sales of fine pitch and high-speed interconnection systems have grown steadily. An interesting reminder is that most high-speed interconnects are also fine pitch. However, the smaller the interconnect pitch, the more difficult it is to achieve higher bandwidth.

Smaller and tighter pitch interconnect systems have brought a series of new electrical challenges, such as crosstalk and insertion loss. This is mainly due to the fact that one differential pair is too close to the next, thereby reducing wiring space and reducing ground pins.

As with many design challenges, there are several ways to solve this problem:

PCB layout

Designers can alleviate these problems by strategically considering the layout of their circuit boards. Carefully planned trace design and routing, grounding positions, vias, etc. can increase the PCB data rate. PCB design strategies are beyond the scope of this article, but there are plenty of tools, resources, and people to assist in this work. For example, Samtec owns Signal Integrity Group and Teraspeed Consulting to help solve these problems.

High-speed fine pitch interconnection design

Although there are conflicts between miniaturization and higher data rate goals, connector manufacturers can strike a balance between performance and footprint.
An example of these connector design strategies is the contact called EdgeRate®. The contact is designed for higher cycle applications while adapting to higher bandwidth. For example, the 0.8mm pitch edge rate interconnect is rated at 56 Gbps PAM4. One way to achieve this balance between bandwidth and spacing is to design and place pins in the plastic body. Specifically, the thin and narrow cutting edges that Edge Rage touches are placed side by side. This minimizes the parallel surface area, which reduces broadside coupling and crosstalk.

Connector design solves data rate and density challenges

Improve connector performance

Other connector design strategies used to achieve high-bandwidth fine-pitch interconnects include, but are not limited to:

・ Perform multiple simulation cycles in the early stages of the design to accurately quantify product performance before starting expensive manufacturing processes.
・ When the connectors are mated, minimize the via stub in the contact area. From a mechanical point of view, the longer the via stub, the better the reliability, but the via stub is an electrical load like an antenna.
・ Simplify contact geometry to improve signal path performance.
・ Shorten the lead length to minimize the distance the signal must travel.
・ Include asymmetrical positions and contacts as much as possible; alternate design reduces paired crosstalk between pin rows and between rows. In other words, the footprint should drive the connector performance.
・ Optimize the connector branch area (BOR). Think of the connector as the key node in the link; focus not only on the node, but also on the link.
・ When space permits, insert a common ground plane into the connector.

Plastic molded products will obviously affect the performance of the connector. Among other issues, we carefully consider the following attributes:
・ High temperature plastic suitable for RoHS
・ Match Dk to obtain the required impedance control
・ Dimensional stability of temperature and time

Most importantly, the shorter and straighter the signal path (contact with the connector), the better the signal integrity performance. But the balance function is that the connector must have sufficient positive force and pull-out force, as well as a certain degree of sturdiness. The latter considerations usually degrade signal integrity performance.

The Links:   NL6448BC26-20F-22 PM300DVA120

Author: Yoyokuo