ADI teaches you how to face the challenges of sensor signal conditioning!

Sensors are everywhere, and they are used to measure temperature, light, sound, and various other environmental parameters. In some applications, the sensor can convert the sample under test into a sensor. For example, colorimeters use LEDs to shine light through a liquid sample to be measured. The light absorption of the sample modulates the amount of light detected by the photodiode in order to reveal the properties of the liquid under test. Blood oxygen content can be determined by measuring the difference between the absorption of red and infrared light in vascular tissue. Ultrasonic sensors measure the airflow rate based on the Doppler shift of the ultrasound traveling through the gas. All of these systems can be implemented using synchronous demodulation.

Sensors are everywhere, and they are used to measure temperature, light, sound, and various other environmental parameters. In some applications, the sensor can convert the sample under test into a sensor. For example, colorimeters use LEDs to shine light through a liquid sample to be measured. The light absorption of the sample modulates the amount of light detected by the photodiode in order to reveal the properties of the liquid under test. Blood oxygen content can be determined by measuring the difference between the absorption of red and infrared light in vascular tissue. Ultrasonic sensors measure the airflow rate based on the Doppler shift of the ultrasound traveling through the gas. All of these systems can be implemented using synchronous demodulation.

ADI teaches you how to face the challenges of sensor signal conditioning!

Figure 1. Synchronous demodulation system

Figure 1 shows a synchronous demodulation system that measures the sensor output signal. The excitation signal fx acts as a carrier and the sensor is modulated with amplitude, phase (or both) as a function of the parameter to be measured. The signal may be amplified and filtered before being down-modulated by a phase sensitive detector (PSD) back to DC. The output filter (OF) limits the signal bandwidth to the frequency range of the parameter under test.
  
Noise at the sensor output can be influenced by internal sources or external coupling. Low frequency (1/f) noise often limits the performance of a sensor or measurement electronics. Many sensors are also susceptible to interference from low-frequency ambient noise. Optical measurements are susceptible to background lighting; electromagnetic sensors are susceptible to power source radiation. Free choice of excitation frequency to avoid noise sources is an important advantage of synchronous demodulation.

Choosing an excitation frequency that reduces the effects of these noise sources is an important way to optimize system performance. The excitation frequency should be chosen with a low noise floor and a sufficient distance from the noise source so that proper filtering can reduce the noise to an acceptable level. Sensor excitation is often the largest piece of the power budget. If the sensor’s sensitivity versus frequency is known, energizing the sensor at a frequency with higher sensitivity reduces power consumption.

02

Phase sensitive detector

To understand the anti-aliasing filter (AAF) and OF requirements, you need to understand the PSD. Consider a PSD that simultaneously scales the input signal by a factor of +1 and C1 by the excitation signal. This is equivalent to multiplying the input signal by a square wave of the same frequency. Figure 2a shows the time-domain waveforms of the input signal, the reference, and the PSD output; in the figure, the input signal is a square wave with an arbitrary phase relative to the reference.

When the input and reference voltages are completely unphase-shifted, the relative phase is 0°, the switch output is DC, and the PSD output voltage is +1. As the relative phase increases, the switching output becomes a square wave at twice the reference frequency, and the duty cycle and mean decrease linearly. When the relative phase is 90°, the duty cycle is 50% and the average value is 0. At 180° relative phase, the PSD output voltage is C1. Figure 2b shows the average output value of the PSD when the relative phase is swept from 0° to 360°, and the input signals are square and sine waves.

ADI teaches you how to face the challenges of sensor signal conditioning!

ADI teaches you how to face the challenges of sensor signal conditioning!

Figure 2. (a) PSD time-domain waveform (b) PSD output average as a function of relative phase

The sine wave case is not as intuitive as the square wave case, but can be computed by multiplying term-by-term and decomposing into addition and subtraction terms, as follows:

ADI teaches you how to face the challenges of sensor signal conditioning!

As expected, the PSD produces a response at the fundamental frequency proportional to the cosine of the relative phase of the input signal, but it also produces a response for all odd harmonics of the signal. If the output filter is considered as part of a phase-sensitive detector, the signal transmission path looks like a series of bandpass filters centered on the odd harmonics of the reference signal. The bandwidth of the bandpass filter is determined by the bandwidth of the lowpass output filter. The PSD output response is the sum of these bandpass filters, as shown in Figure 3. The portion of the response that appears on the DC side falls within the passband of the output filter. Parts of the response that appear at even harmonics of the reference frequency will be suppressed by the output filter.

ADI teaches you how to face the challenges of sensor signal conditioning!

Figure 3. Signal input spectrum contributing to PSD output

At first glance, the infinite summation aliasing of harmonics into the output filter passband seems to invalidate this approach. However, the effects of noise aliasing are mitigated because each harmonic term is scaled down and the harmonic noise is added as the square root of the sum of the squares. Assuming that the noise spectral density of the input signal is constant, the noise effects of harmonic aliasing can be calculated.

Let Vn be the integrated noise of the transmission window centered on the fundamental frequency. The total RMS noise VT is:

ADI teaches you how to face the challenges of sensor signal conditioning!

Use the convenient formula to sum geometric series:

ADI teaches you how to face the challenges of sensor signal conditioning!

The amount of RMS noise increase due to the harmonic window is:

ADI teaches you how to face the challenges of sensor signal conditioning!

Therefore, the RMS noise generated by all harmonic windows adds only 11% (or 1dB) to the total noise. The output is still susceptible to bandpass filter passband fluctuations, and sensor or electronics harmonic distortion before the PSD will cause errors in the output signal. If these harmonic distortion terms are unacceptably large, antialiasing filters can be used to reduce them. Antialiasing and output filter requirements will be considered in the next design example.

03

LVDT Design Example

Figure 4 shows a synchronous demodulation circuit that extracts position information from a Linear Variable Displacement Transformer (LVDT, a special type of wire-wound transformer with an active core that is affixed to the location to be measured). The excitation signal is applied to the primary side. The secondary-side voltage varies proportionally with the core position.

There are many types of LVDTs, and the methods for extracting location information also vary. The circuit uses a 4-wire mode LVDT. The subtraction is performed by connecting the secondary outputs of the two LVDTs with opposite voltages. When the LVDT core is at the zero position, the voltages on the secondary are equal and the voltage difference across the windings is zero. As the core moves from the zero position, the voltage difference across the secondary winding also increases. The LVDT output voltage sign changes depending on the direction. The LVDT chosen for this example measures ±2.5 mm full-scale core displacement. The voltage transfer function is 0.25, meaning that when the core is 2.5 mm off center, the differential output per volt applied to the primary is equal to 250 mV.

ADI teaches you how to face the challenges of sensor signal conditioning!

Figure 4. Simplified LVDT position detection circuit

04

Integrated Synchronous Demodulator

The ADA2200 integrated synchronous demodulator uses a unique charge sharing technique to perform discrete time signal processing in the analog domain. The device’s signal path consists of an input buffer, an FIR decimation filter (for anti-aliasing filtering), a programmable IIR filter, a phase-sensitive detector, and a differential output buffer. Its clock generation function synchronizes the excitation signal with the system clock. Programmable features are configurable through an SPI-compatible interface.

ADI teaches you how to face the challenges of sensor signal conditioning!

Figure 5. ADA2200 Synchronous Demodulator

The 4.92 MHz clock generated by the AD7192, a 24-bit sigma-delta ADC, is used as the master clock. The ADA2200 generates all the internal signals required for the filter and PSD clock, in addition to generating the excitation signal on the RCLK pin. The device divides the master clock by 1024 to generate a 4.8 kHz signal that controls the CMOS switches. A CMOS switch converts the low noise 3.3 V source into a square wave excitation signal for the LVDT. The 3.3 V supply used for the excitation source is also used as the ADC reference, so any drift in the voltage source will not degrade the measurement accuracy. At full-scale displacement, the LVDT outputs a 1.6 V peak-to-peak output voltage.

05

Anti-aliasing filtering

The RC network between the LVDT output and the ADA2200 input provides low-pass filtering of the LVDT output signal while creating the relative phase shift needed to maximize the demodulator output signal. As mentioned earlier, Figure 2b shows that the maximum PSD output occurs at a relative phase shift of 0° or 180°. The ADA2200 has 90° phase control, so a ±90° relative phase offset can also be used.

Signal energy at odd multiples of the demodulation frequency will appear in the passband of the output filter. The FIR decimation filter implements anti-aliasing filtering that provides at least 50 dB of attenuation for these frequencies.

An IIR filter can provide additional filtering or gain if required. Since the IIR filter is in front of the phase sensitive detector, its phase response will affect the output bandwidth of the PSD signal. This must be taken into account when designing the filter response.

06

output filter

The passband of the output filter should be chosen to match the bandwidth of the parameter under test, but limit the broadband noise of the system. The output low-pass filter must also be able to reject output spurs generated by even multiples of the PSD.

ADI teaches you how to face the challenges of sensor signal conditioning!

This circuit uses the LPF built into the AD7192, a sigma-delta ADC. It can be programmed to achieve a sinc3 or sinc4 response, and the transfer function is zero at multiples of the output data rate.

Setting the ADC’s output data rate to the demodulation frequency suppresses PSD output spurs. The programmable output data rate of the ADC acts as a selectable bandwidth output filter. The available output data rate (fDATA) is 4.8 kHz/n, where 1 ≤ n ≤ 1023. Therefore, the ADC averages the output of the demodulator over n demodulation clock cycles for each output data value. Because the host clock and ADC clock are synchronized, the zeros of the ADC output filter transfer function will fall directly on every harmonic of the modulation frequency and suppress all output spurs for any value of n.

Figure 6 shows the sinc3 transfer function normalized to the ADC output data rate.

The programmable output data rate has an intuitive trade-off between noise and bandwidth/settling time. The output filter noise bandwidth is 0.3 × fDATA, the 3 dB frequency is 0.272 × fDATA, and the settling time is 3/fDATA.

At output data rates up to 4.8 kHz, the ADC digital filter has a 3 dB bandwidth around 1.3 kHz. Up to this frequency, the RC filter between the demodulator and ADC is relatively flat, minimizing the ADC’s bandwidth requirements. In systems with lower maximum data rates, the RC filter corner frequency can be scaled down.

07

Noise performance

The output noise of this circuit is a function of the ADC output data rate. Table 1 shows the effective number of bits of digitized data relative to the ADC sampling rate, assuming a full-scale output voltage of 2.5 V. Noise performance is independent of LVDT core location.

ADC data rate (SPS)

output bandwidth

(Hz)

ENOB (rms)

4800

1300

13.8

11.3

1200

325

14.9

12.3

300

80

15.8

13.2

75

20

16.2

13.5

Table 1. Noise Performance vs Bandwidth

If the ADA2200 output noise is independent of frequency, the effective number of bits is expected to increase by one bit for every 4× decrease in the output data rate. ENOB does not rise as much at lower output data rates due to the 1/f noise of the ADA2200 output driver; this noise dominates the noise floor at lower output data rates.

08

Linearity

Linearity results are measured first by performing a two-point calibration at ±2.0 mm core displacement. From these measurements, the slope and offset can be determined for the best straight line fit. Then, the core displacement is measured over a ±2.5 mm full-scale range. Linearity error can be determined by subtracting the measured data from the straight line data.

ADI teaches you how to face the challenges of sensor signal conditioning!

Figure 7. Position Linearity Error vs. LVDT Kernel Displacement

The E-Series LVDTs used for circuit evaluation have a linearity rating of ±0.5% (±2.5 mm displacement range). The circuit performance exceeds the specifications of the LVDT.

09

Power consumption

The total circuit power dissipation is 10.2 mW, including 6.6 mW driving the LVDT and 3.6 mW for the rest of the circuit. Circuit SNR can be improved by increasing the LVDT excitation signal, but at the expense of higher power consumption. Alternatively, power consumption can be reduced by lowering the LVDT excitation signal, while a low-power dual op amp is used to amplify the LVDT output signal in order to preserve the circuit’s SNR performance.

The Links:   6MBI75U2A-060 2MBI400L-060

Author: Yoyokuo