“Motor drive Motor drive is a general term for the miniature motor or spring and its accessories assembled in the film camera. With the help of the miniature motor, the film is automatically reeled, most of which are used in 35mm single-lens reflex cameras.
Motor drive Motor drive is a general term for a micro motor or spring and its accessories assembled in a film camera. With the help of a micro motor, the film is automatically reeled, most of which are used in 35mm single-lens reflex cameras.
01 Principle of power supply circuit
The schematic diagram of the power supply part is shown in Figure 1-1:
It can be known from Figure 1-1 that there are three types of power supplies: +5V, +3.3V, and +1.5V, and each power supply has a 0.1µF bypass capacitor to bypass the high-frequency crosstalk in the power supply to ground to prevent high Frequency signals crosstalk into other modules through the power supply. At the same time, the power frequency interference of the power supply itself can be filtered out.
It is worth noting that when wiring, the power output point after decoupling by the decoupling capacitor should be as close as possible to the power supply pin of the chip for power supply, and the too long lead may become an interference receiving antenna again, resulting in the decoupling effect. disappear. If it is impossible to make each power output point after decoupling be close to the power pin of the chip, then the method of decoupling can be used separately, that is, connect the decoupling capacitor as close as possible to the power pin of each chip for decoupling. This also explains why the 3.3V power supply in Figure 1-1 has two decoupling output points.
02. Principle of motor drive circuit
The principle of the motor drive circuit is shown in Figure 2-1:
In Figure 2-1, Header 4X2 are 4 rows and 2 columns of pins, FM0~3 are FPGA chip I/O output ports, the added pins give a movable mechanism, and they are connected with jumper caps when they are needed. Improve the use efficiency of I/O ports. RES5 is a five-port resistance exclusion. It integrates 4 resistors of equal resistance and one end is connected in common. PIN 1 is the common end, and PIN2~5 are the output ends of the resistance exclusion. The schematic diagram of the resistance exclusion is shown in Figure 2-2:
The common terminal of the exclusion is connected to the power supply, that is, in the form of a pull-up resistor. Its function is to enhance the driving capability of the I/O port (hereinafter referred to as the I/O port) of the FPGA chip. In fact, it is to increase the output current when the I/O outputs a high level. . When the I/O outputs a high level, the +5V power supply is connected to IN1~4 through the exclusion resistor, which is equivalent to providing an additional current output source for the I/O, thereby improving the driving capability. When I/O outputs low level, I/O can be regarded as grounding approximately, and because IN1~4 are directly connected with I/O by wires, they directly receive the low level output signal of I/O. At this time, the +5V power supply is grounded after the resistance R and the internal circuit of the I/O (resistance is approximately zero), so the current of this circuit cannot be greater than the maximum current (Ii) of the I/O, there is formula 2-1:
The value range of exclusion can be obtained from formula 2-2.
In addition to improving the driving ability, the pull-up resistor also has another function, which is to perform level conversion. After investigation, the interface logic of ULN2003 is: 5V-TTL, 5V-CMOS logic. In the case of 3.3V power supply, the I/O port can provide 3.3V-LVTTL, 3.3V-LVCMOS, 3.3V-PCI and SSTL-3 interface logic levels. Therefore, an external 5V pull-up resistor is required to change the I/O level specification to 5V level logic.
The chip ULN2003 integrates 7 groups of Darlington tubes, which are specially used to improve the driving current. The logic between the chip pins is shown in Figure 2-3:
Since the I/O current is far from enough to drive the motor, it is necessary to connect the chip to drive the motor. The Darlington tube circuit integrated in the ULN2003 is shown in Figure 2-4. The form of Darlington tube has the characteristics of converting weak signals into strong electric signals. The I/O level logic is input from PIN IN, and the strong electric signal input at the PIN 9 (COMMON) terminal is controlled by the Darlington tube according to the I/O The signal changes regularly. It is worth noting that the output logic of ULN2003 will be opposite to the input logic, and this feature should be paid attention to when programming.
RES6 is a six-port resistance exclusion. It integrates 5 resistors of equal resistance and one end is connected in common. PIN 1 is the common terminal, and PIN2~6 are the output terminals of the exclusion. For the schematic diagram and connection description, please refer to the above Figure 2- 2. See formula 2-2 for the calculation of the exclusion value range, which will not be repeated here. It is worth noting that: PIN 1 of RES6 is connected to PIN 2 because there is an extra resistor that is not used. In order to avoid PIN 2 hanging in the air, PIN 2 is connected to PIN 1 (common), that is, the resistor corresponding to PIN 2. is shorted to both avoid a floating pin and disable the resistor.
03 The principle of the motor indicator light circuit
The motor indicator circuit is shown in Figure 3-1:
The indicator lights of the motor part are used to indicate the logic level status of each signal, among which R106~109 are current limiting resistors to prevent the LEDs from being burned due to excessive current. It is worth noting that the light-emitting diode of the indicator is connected to a common anode, and the M0~3 signal port generates a low level to light up the corresponding diode, while the OUT and IN logic levels of ULN2003 are opposite, so for the I/O port FM0 For ~3, outputting a high level can light up the corresponding LED. For example, if FM0 outputs a high level, the corresponding LD17 lights up. When programming, it should be noted that this circuit inverts the actual logic of the I/O twice. The corresponding relationship is which channel of high level output from the I/O port corresponds to which channel of indicator light is lit.
04 Principle of clock circuit
The clock circuit is shown in Figure 4-1:
The 50Mhz active crystal oscillator is used to generate the clock signal, and the connection method adopts the typical connection method of the active crystal oscillator: PIN 1 is suspended, PIN 2 is grounded, PIN 3 outputs the clock signal, and PIN 4 is connected to the power supply. Since the I/O power supply of the FPGA is 3.3V, and the clock signal generated by the clock circuit must be received by the I/O port, the maximum value of the clock signal cannot exceed 3.3V, so the clock circuit power supply is powered by 3.3V.
05FPGA part of the circuit principle
The schematic diagram of part of the FPGA circuit is shown in Figure 5-1:
Header 18X2 is an array of 18 rows and 2 columns. The two arrays are connected to the PIN port, 3.3V power supply, and digital ground respectively. It provides a movable mechanism, so that the PIN port can be connected to the target with a cable as needed to achieve signal transmission. the goal of. The 3.3V power supply and the digital ground pin can be used to provide a logic high level or a logic low level for the target with a cable as needed.
U21D is the clock signal receiving part of the FPGA chip, and is connected to the corresponding clock signal port through the network label “CLK0~3”.
U21C is the power supply and grounding part of the FPGA chip. The port with the word “GND” is the “ground” port, which is connected to the digital ground. VCCIO1~4 are the power supply ports of the I/O port, which are powered by 3.3V power supply and pass the network label “+3.3 V” is connected to the 3.3V power port. VCCA_PLL1, VCCA_PLL2, and VCCINT are the power supply ports of the internal arithmetic unit and input buffer. They are powered by 1.5V power supply and are connected to the 1.5V power supply port through the network label “+1.5V”.
U21B is the download part of JTAG and AS, TMS, TCK, TD1, TD0 are the mode selection terminal, clock signal terminal, data input terminal and data output terminal of JATAG download mode respectively. DATA0 is the data port downloaded by AS, MSEL0, MSEL1, nCE, nCEO, CONF_DONE, nCONFIG, nSTATUS ports are connected according to the typical connection method. It is worth noting that both AS and JTAG communicate through the JTAG standard. AS download is generally to download POF to the PROM (flash), which can still be loaded after re-powering. JTAG download is to directly download the sof file to the FPGA through the JTAG port. , is generally used for temporary debugging, and it will be lost after power failure.
U22 is an electrically erasable ROM, which is used to store the data downloaded by AS, so that the program segment of the FPGA can be saved even when the power is turned off. The DATA terminal is the data reading terminal, which is used to read the data in the ROM. DCLK is the clock port, which is used to receive the clock signal for synchronous transmission. nCS is the chip select port, which is used to receive the chip select signal to communicate with the chip. ASDI is the AS download data input terminal for receiving AS download data. VCC and GND are the power port and the ground port respectively, which are connected to 3.3V and digital ground respectively.